Making the Little Things Count on Your PCB Design

October 8, 2018 John Burkhert

Even as everything related to electronics shrinks in size, a few small areas that we have been able to ignore so far remain. Along with the physical reduction, we also encounter reductions in our timing budgets, power consumption, and EMI – spelled out as electromagnetic emissions. Doing more and, doing it faster and more efficiently with a minimum PCB outline, creates a conundrum of opposing requirements. Getting our products to pass all of the initial tests as well as the ultimate test of surviving and thriving in the field often comes down to some seemingly insignificant attributes.

Incorporating pin-delay in your timing constraints adds elegance and accuracy to the design. The larger the SOC, (System On Chip) the more this matters.

Put on your VR goggles and shrink yourself down to join me inside the device package. At our feet, we may find a grid of circular pins where all of the signals come and go. Above us is a cap attached to a seal ring to keep the negative waves at bay and to keep our spurious signals from leaking out. An entire system resides between the pins and the cap. One or more semiconducting dice are doped with millions, if not billions, of transistors. The die are placed in small cavities in the substrate in one of two ways. Flip-chips work like the BGA in miniature. They are placed and soldered down. In many cases lead solder is still used in small amounts simply because we have not invented a eutectic solder with the same properties.

Another die attach method features a solid ground plane on the bottom of the semiconductor which is bonded to the bottom of the cavity using epoxy. Tiny wire bonds reach across the divide and land on the substrate. In either of these cases, flip chip or wire bond, there is likely to be some fan-out. This will naturally lead to some length variance as the outer corner pins will be farther from the die than those along the inner rows. This leads to so-called pin-delay. When we are length-matching traces down to the thousandths of an inch, these little segments come into play. Note that the corner pin is also likely to have a shorter path to the receiver pin since it starts at the perimeter of the device rather than deep inside. This geometry will tend to wash out the wrinkles.

 

Image credit: Author - a measurable amount of skew can take place on the device.

 

Accounting for this difference serves two purposes. One, we can get by with a little less meander as the longest lines on the board may have the shortest lines on the package. That part cleans up routing. Further, we have refined our timing budget for each net bringing the overall system into tighter tune. Incorporating pin-delay in your timing constraints adds elegance and accuracy to the design. The larger the SOC, (System On Chip) and, the faster it runs, the more this matters.

Diving into the Core of the Board

Another performance upgrade to consider is what happens when we change layers. In addition to the impedance discontinuity, the via also takes precious nanoseconds for the signals to traverse. I’ve had chip-makers approach the DDR section of the layout in a way that the majority of the members of a byte lane could be routed on the top layer. But then, the clock pair and the DATA3 net were placed well inside the SOC requiring inner layer routing. The layer count was insufficient to bury all of the lines that launch from the edge of the device. What was I supposed to do? That’s an easy one. Bring the stakeholders together and lay the problem on the table. We had to calculate the paths based on actual propagation times rather than raw trace length. The constraints became a little more interesting while I learned something new about sympathetic vias.


 

Image credit: Circuit Insight - Showing the three typical types of transmission lines.

The physics of the outer layers slow the microstrip signals down while the internal stripline signals propagate down the trace about 10% faster. The exact ratio varies by material and geometry. Surface roughness is the new/old hot topic. Just know that the outer layer signals will also radiate more energy. By the way, radiation isn’t magical free energy. It is parasitic, turning your limited power into unwanted noise. We can’t afford that. Bottling those waves up inside a Faraday cage of ground planes and vias is usually the better choice.

It’s an Analog World After All

We can justify outer layer traces in the analog domain by keeping them as short as possible from one surface mount part to the next in a clothesline arrangement. The essential takeaway is that the routing drives the placement rather than the other way around. Vias make the analog engineers uneasy. A long RF trace should probably be buried anyway. Save power and reduce emissions so the product passes the FCC requirements; win/win.

The clothesline placement of the RF chain is done in a way that eliminates or at least reduces the presence of stubs. A shunt cap added onto a crowded chain might end up being placed next to the transmission line and routed with a really short trace. No good. The signal sees this little branch as though the trace suddenly got much wider – and much lower in impedance as a result. Stubs are sometimes necessary to tune a circuit, but unwanted stubs can tank an otherwise sound analog layout. Do whatever you have to do to get rid of any of those stubs in your placement.

If you can match the width of the typical pad to the transmission line, you get rid of another impedance mismatch. That can mean wider traces which will drive thicker dielectric material. If you are using micro-vias, that is probably not an option because of the aspect ratio requirements of the micro-via. Smaller parts are the choice for signal integrity in that case. Everyone wants the smaller parts, so supply and demand = they cost more. If you must run a narrow trace to a wide pad, add a fillet at the junction to smooth things out. Then explore opening the ground plane under the component pad and then add a reference ground on the next layer down. Use all of your free tricks and tools before splurging on special materials or components.

In Closing...

Accounting for the circuit integrity beyond the traces and shapes, we look at the device parameters as well as the Z-axis channels on the PCB. Backdrilling away any z-axis stubs on the thicker backplanes or being mindful of placement of the analog block will bring the many pieces together as one functional unit. Each element is interrelated to the others, and there are always trade-offs to consider. We are sometimes faced with two unappealing choices. Choosing and mitigating the effects of the least problematic choice is a skill that comes with time. The more you see, the more you know. Keep your eyes open. The truth is out there.

 

About the Author

John Burkhert

John Burkhert Jr is a career PCB Designer experienced in Military, Telecom, Consumer Hardware and lately, the Automotive industry. Originally, an RF specialist -- compelled to flip the bit now and then to fill the need for high-speed digital design. John enjoys playing bass and racing bikes when he's not writing about or performing PCB layout. You can find John on LinkedIn.

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