High-Speed Design

  • Constraints in DDR Routing: The Expansive Power of Limits

    Constraints in DDR Routing: The Expansive Power of Limits

    Constraints in DDR routing enable a designer to manage tricky layout considerations with ease.

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  • DC Voltage Requirements for Electronic Devices on High-Speed PCBs

    DC Voltage Requirements for Electronic Devices on High-Speed PCBs

    The DC voltage requirements for electronic devices on high-speed boards present design challenges that are best overcome with design-analysis integration.

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  • Understanding the Different PCB Layer Configurations for Microstrip vs Stripline

    Understanding the Different PCB Layer Configurations for Microstrip vs Stripline

    Knowing the differences between microstrip vs stripline routing methodologies will help you to set up your board for the best high speed routing configurations.

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  • Tips for Optimal High Speed SPI Layout Routing

    Tips for Optimal High Speed SPI Layout Routing

    High speed SPI layout routing helps achieve faster data transfer between microcontrollers and peripherals. Avoid suboptimal design with these tips.

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  • USB PCB Routing Tips for Peak Reliability and Performance

    USB PCB Routing Tips for Peak Reliability and Performance

    USB routing tips will consider many traditional routing methods with a tighter focus on power supply and EMI in your USB.

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  • Guide on PCB Trace Length Matching vs Frequency

    Guide on PCB Trace Length Matching vs Frequency

    Understanding PCB trace length matching vs frequency means knowing at what point you can operate propagation delay within expected or necessary signal integrity.

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  • Energy in Inductors: Stored Energy and Operating Characteristics

    Energy in Inductors: Stored Energy and Operating Characteristics

    In order to know the energy in inductors, simulation and model parameters can go a long way to give your designs added security.

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  • Serpentine Routing Tips to Snake in Your Tuned Traces

    Serpentine Routing Tips to Snake in Your Tuned Traces

    In today’s high speed PCB designs, measured and matched length traces must be accurate. Here are some tips on how to automatically add this serpentine routing.

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  • MII and RMII Routing Guidelines for Ethernet

    MII and RMII Routing Guidelines for Ethernet

    Designing an Ethernet-capable device? You’ll need to familiarize yourself with MII and RMII routing guidelines. Learn more from Cadence.

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  •  CPLD vs. FPGA: Which Do You Need For Your Digital System?

    CPLD vs. FPGA: Which Do You Need For Your Digital System?

    With the popularity of NAND and NOR gates, it can be easy to overlook the capabilities of CPLD vs FPGA when looking to satisfy the needs of your digital system.

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  •  EMI and Safety: Hazards, Risks, and Designing to Avoid Them

    EMI and Safety: Hazards, Risks, and Designing to Avoid Them

    Understand the impact of EMI on circuit reliability and critical safety applications.

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  • PCB Design Techniques to Reduce Ground Bounce in Signal Integrity

    PCB Design Techniques to Reduce Ground Bounce in Signal Integrity

    Switching noise can cause problems in your PCB design. Here are some suggestions for how you can reduce ground bounce in signal integrity on your next design.

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  • How Current Density In PCB Trace Can Affect Functionality

    How Current Density In PCB Trace Can Affect Functionality

    Current density PCB traces can accumulate can affect the overall health of your design as well as subject your device to errors like overcooking and shortages.

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  • Working with High Speed and RF PCB Trace Lengths in Your Design

    Working with High Speed and RF PCB Trace Lengths in Your Design

    Here are some PCB routing best practices to use when working with high speed and RF PCB trace lengths in your design to avoid signal integrity problems.

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  • Achieving PCI-e Compliance: Getting It Right the First Time

    Achieving PCI-e Compliance: Getting It Right the First Time

    The PCI-e protocol is complex and to meet PCI-e compliance for the electrical category of the Physical Layer, several tests must be run encompassing several categories.

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  • Notes on Near Field Communications

    Notes on Near Field Communications

    NFC is a touch-and-go standard for sharing a few packets of data with another device that is in close proximity. How close? Centimeters. The small broadcast and...

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  • The Ethernet is Coming For Your Ride

    The Ethernet is Coming For Your Ride

    Automotive Ethernet. It really is a thing. Our cars will have to outsmart our phones if we’re going to hand over the reins in any meaningful (and safe!) way....

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  • Tips for Routing Mixed Signal PCBs

    Tips for Routing Mixed Signal PCBs

    Designing a PCB correctly requires designers to consider a myriad of elements; overall layout (component spacing, placement,...

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  • DDR Bus Design for PCB Engineers

    DDR Bus Design for PCB Engineers

    Last summer, Cadence and Micron prototyped the first IP interface in silicon for a preliminary version of the DDR5-4400 IMC. The new chip...

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  • Techniques for Optimizing Return Paths

    Techniques for Optimizing Return Paths

    First of all, what is a return path? The ground plane is the simple answer. For every wave of energy (measured in volts) that goes out from a source, an...

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