Refrigerator magnet poetry is one of my favorite parts of other peoples’ houses. Getting the opportunity to leave silly, coded messages to others or mix-and-match some funny sounding nonsense will always get me laughing. The market has definitely grown in the past few years, though, with a horde of themes available. Choosing between which magnets to use for the best language mixtures can get tedious with great choices like apocalypse, bacon, grouchy cat, and math lover. Unfortunately, not all logic arrays are as fun to think through as fridge magnet poetry.
PAL, SPLD, CPLD, FPGA, ASIC… the alphabet soup of programmable logic devices and signalling standards is extensive. Choosing between a Complex Programmable Logic Device (CPLD) vs. Field-Programmable Gate Array (FPGA) depends on the application surrounding your design, and there are plenty of options on the market. Let’s take a look at the tradeoffs between CPLDs and FPGAs.
Using CPLD vs. FPGA Integrated Circuits
Although all digital logic circuits can be formed from creative combinations of NAND and NOR gates, using individual NAND and NOR 7400 ICs is prohibitive for creating programmable logic circuits. Using a CPLD or FPGA for programmable logic is often a better choice as you have a broader range of functionality in a smaller footprint.
Most CPLDs implement sum-of-product combinatorial logic and optional flip-flops for logic operations. The use of combinatorial logic function supports wide fan-in. For this reason, a CPLD with a large number of inputs may be a better choice than an FPGA with a low number of I/O pins and for simpler applications. In terms of the number of logic blocks, an FPGA can contain around 100,000 logic blocks while a CPLD only contains thousands. This means FPGAs can be specialized for more complex computation and applications.
CPLDs are programmable using an electrically erasable programmable read-only memory (EEPROM), so their configuration is stored in non-volatile memory and can be accessed even after a reboot. In contrast, FPGAs are static random access memory (SRAM)-based and the bitstream must be fed to the device from external non-volatile memory. One typical use case for a CPLD is to configure an FPGA when a system is booted. However, major chip makers are designing the next generation of FPGAs to have non-volatile memory, eliminating the need for an external module.
The reconfigurable nature and complicated architecture of an FPGA makes their signal processing delay unpredictable. Simply counting the number of operations executed within your FPGA is not sufficient for predicting delay. In contrast, CPLDs have much lower pin-to-pin delay for the same switching frequency due to their simpler architecture. This is quite important to consider if you need to synchronize parallel data across different signal nets.
Knowing which and how to use your CPLD and FPGAs could save you countless hours in the future
Signal Integrity and Thermal Management
Older CPLDs families consumed enough power to make them prohibitive in applications requiring battery power. Today’s newer CPLDs are more power efficient, making power consumption in battery powered devices and thermal management less of an issue.
In comparison, an FPGA running at full clock speed and switching at high frequency requires some level of thermal management; such as a passive heat sink or more intensive active methods, like using a fan or even an evaporative heat exchanger. At the board level, you’ll need to determine the best thermal management strategy in order to keep the board temperature below the junction temperature.
In terms of actual switching frequencies, many FPGAs and CPLDs have clock blocks with phase locked loops (PLLs) and/or delay locked loops (DLLs) for frequency synthesis. This allows the clock frequency to be multiplied to a higher value as required for certain tasks. Note that this can exacerbate already problematic thermal problems; it may be a good idea to include a switchable fan that turns on when the clock frequency and/or chip temperature exceed certain values.
When including either a CPLD or FPGA in your board, the switching speed in either device will determine whether your signals will produce transmission line behavior in your traces. Here, the actual switching speed is the important parameter, not the data rate. Rather than impedance matching each output trace from these devices individually, you’re better off implementing controlled impedance design throughout your board to ensure traces are properly terminated.
Single-ended signalling is fine for simple applications, but advanced applications involving high speed and/or longer traces should use a differential signalling standard. The common differential signalling standards for CPLDs and FPGAs are low voltage differential signaling (LVDS), current mode logic (CML), and low voltage positive emitter coupled logic (LVPECL). You’ll need to program your IC and design your schematic/layout around the desired signalling standard.
ASICs have become massively popular in cryptocurrency miners
Going Further With ASICs
Although you’re probably not reading this article on a device that uses an FPGA, they are likely to become more ubiquitous in smartphones and computers for artificial intelligence and machine learning applications. The reconfigurable nature of these chips provides dedicated processing for complex algorithms without consuming computing resources that are dedicated for basic functionality in these devices.
Until FPGAs are optimized for mass production, they are likely to remain a rarity in most devices. If you’re looking for high speed, lower cost, and lower power consumption, an application specific integrated circuit (ASIC) may be a better choice. You’ll sacrifice adaptability, but you’ll win with lower costs for high volume device runs.
The drawback with using ASICs is the required initial investment. Because the hardware is not reconfigurable, you’ll have engage with a foundry to fabricate and package your ASIC. However, after the initial NRE costs, ASICs have a lower cost per unit to produce, making them a better choice for high volume production.
The right PCB design and analysis software from Cadence includes a full suite of simulation tools that can help you identify and correct signal, power, and thermal management issues in your boards. The FPGA development tools help you move through the development process while remaining DO-254 compliant. Try working with the Allegro SI toolkit for your next CPLD or FPGA-based system.
If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.
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