Are you ready for terabit Ethernet? You’ll need decision feedback equalization...
When you talk to most PCB designers about digital signaling, they are used to working with two signal levels: HIGH and LOW. This works just fine for most applications, including moderate speed networking. However, when you move to 100Base and faster data rates, multi-level signaling (MLS) schemes and encoding schemes become critical for ensuring sufficient data can be transferred through a data link.
At the 1000Base level and beyond, equalization schemes become critical for ensuring data can be accurately extracted from MLS. These systems experience significant inter-symbol interference (ISI) and jitter, as well as being susceptible to problems of noise. Among the popular equalization schemes used for high speed data links, decision feedback equalization is one popular scheme for estimating the signal level in the presence of various noise sources. As the world moves to 400 Gb/s and beyond, decision feedback equalization and related schemes will be critical for working with data links that use advanced MLS schemes.
MLS Schemes Used in High Speed Data Links
Before jumping into decision feedback equalization, it is important to understand some important aspects of MLS schemes, particularly pulse amplitude modulation (PAM) schemes, which are used in 10Base and faster Ethernet links.
The following graph shows how signals are encoded in non-return to zero (NRZ), the standard signaling method used in most digital ICs, and PAM-4, which is an MLS. By dividing the full output voltage range into 4 levels, PAM-4 allows 2 bits to be transmitted within each unit interval (UI), effectively doubling the data rate compared to NRZ. Note that the signal levels in PAM-4 or other MLS PAM schemes can be assigned to any combination of bits using Gray code.
NRZ vs. PAM-4 signaling
Even in PCBs that run at high MHz or GHz data rates, designers are generally stuck with NRZ (sometimes confused with 2PAM) signaling because this is how the components they use operate. There is no carrier wave, and the signal only occupies two possible levels (HIGH and LOW). Designers normally focus on proper layout techniques to provide the required level of noise immunity specified in various signaling standards.
However, equalization schemes have been used to provide jitter/noise immunity to digital signals running high data rates on FR4 when interconnects span beyond the recommended maximum length. A recent example was examined with USB 3.0, where a simple equalization scheme was used with the standard NRZ inverted (NRZI) signaling. NRZI signaling (where logic levels are encoded using signal transitions rather than signal levels) was found to be robust against jitter and did not require complex adaptive equalization schemes to ensure signal integrity.
The presence of noise at the board level and the transceiver level becomes problematic in MLS PAM schemes. For a given maximum signal level (e.g., 5 V), the noise margin for each signal level starts to become comparable to the difference between signal level as more levels are added. While a 0.5 V noise margin may be fine with standard TTL logic, this is unacceptable when working with MLS schemes like PAM-4. Add to this jitter/skew and the noise floor in the system, and your system is at risk of higher BER than the same system operating with NRZ. In general, MLS schemes require higher SNR than the same system operating with NRZ.
At this point, you have two choices to ensure data can be accurately extracted with an MLS scheme. First, you can just run the system at a higher signal level. This exacerbates the problem of ISI, which is proportional to the signal level and adds to noise seen at the receiver. The other option is to use an equalization technique to estimate the signal level. This is where decision feedback equalization comes into play.
Introducing and Importance of Decision Feedback Equalization (DFE)
Equalization has many forms, but the goal in any equalization scheme is signal correction. Decision feedback equalization (DFE), continuous-time linear equalization (CTLE), and feed-forward equalization (FFE) are the dominant equalization schemes used with PAM-4 in 400 Gb/s Ethernet.
Any signal that is transmitted through a channel (whether copper traces or a fiber optic cable) will experience some distortion due to the finite bandwidth (i.e., transfer function) of the channel. In particular, the response of the channel to the rise/fall of a digital signal (i.e., an impulse) creates transients that interfere with the signal level, leading to ISI. Equalization is intended to compensate for this distortion/ISI and extract the desired signal in the presence of noise.
Implementing decision feedback equalization requires building on linear feedback equalization (IFE), which reproduces the transmitted signal after measuring the transient response and calculating its Laplace transform. The limitation of IFE is that it may result in noise gain, where the filtered noise is actually more intense than the unfiltered noise. It also only accounts for ISI between the current and previous bit. However, adding the distributed feedback equalization circuit will correct ISI between the remaining symbols. A block diagram of this scheme is shown below, where R(t) is the received signal and S(t) is the original sent signal.
Distributed feedback equalization circuit block diagram
The “taps” in the LFE and DFE are finite impulse response (FIR) filters. The output from the distributed feedback equalization circuit e(t) is equal to the circuit’s transient response to a sudden change between two voltage levels, i.e., S(t). In terms of the received signal and (M-1) previously received signals, the output is given by:
Distributed feedback equalization output
From here, we can see that S(n) can easily be determined from all other sent signals and the received signals and the tap values. In effect, adding the distributed feedback equalizer as an M-tap filter allows the tap value in each FIR in the DFE to be tuned to the correct value to provide sufficient noise and ISI removal. Note that the delay is equal to an integer multiple of the bit period, thus the delay line should be very precisely designed.
The goal in designing a distributed feedback equalizer is to set the tap values such that a reference signal that uses your desired modulation scheme can be accurately reproduced. The tap values can be determined from simulations or measurements by simply iterating through different tap values and comparing the input and output.
The goal is to minimize and differences between the reference signal and the output from the decision feedback equalization circuit. The two standard optimization methods used here are least mean square error and minimum mean square error. Taps can also be set dynamically using their own feedback circuits, known as adaptive equalization.
If you’re designing complex high speed data links that use MLS, you’ll need to include an equalization scheme. Using the right PCB design and analysis software package allows you to implement and analyze a decision feedback equalization circuit or any other equalization scheme. Allegro PCB Designer and Cadence’s full suite of analysis tools make equalization tasks and other important analyses easy.
If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.
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