Using a PDN Topology Simulation for Power Integrity Analysis

November 18, 2019 Cadence PCB Solutions

Capacitors on a VRM

These capacitors are fundamental in any PDN topology simulation

 

Power integrity used to be an afterthought in PCB design until TTL logic families started causing signal integrity problems in many boards. Signal integrity problems and power integrity are intimately related subjects; one can influence the other thanks to the deeply interconnected nature of any PCB. Some fundamental power integrity problems can be averted with some simple, yet important design considerations, and these design choices can be validated directly from your schematic.

A real PDN topology simulation shouldn’t be confined to examining circuit behavior in a schematic. Parasitics in your layout will affect the behavior of a real PDN. The goal in a PDN topology simulation verifies that your PDN design provides a flat target impedance over a broad range of frequencies. Some of the parasitic effects in any PDN can be accounted for at the schematic level, giving you a baseline for further analyzing your PDN.

Target PDN Impedance

Thanks to parasitics in your board, a PDN is only purely resistive when powered with a DC voltage. A real PDN has some impedance due to parasitics in the board. Real PCBs use bypass/decoupling capacitors to ensure power and signal integrity, which also affects the impedance of a PDN. Even if a PDN is run at DC, real DC power supplies have some ripple (or switching noise in the case of switching regulators), and the current these noise sources propagate into a PDN depend on the PDN’s impedance.

When a digital IC switches, the regulator needs to supply some extra current (up to its maximum output) so that the IC can supply its output current to downstream components. This switching action creates a transient oscillation, which can be seen as a voltage ripple on the power rails in the PDN. The goal in PDN design is to set the PDN’s impedance to a target value so that the ripple is limited below some particular value (expressed as a percentage of the desired supply voltage). The allowed ripple should be chosen based on the noise margin in your downstream components. The target impedance value can be defined as:

 

Target impedance in a PDN topology simulation

Target impedance of your PDN

 

Because the PDN’s impedance is determined in part by parasitic inductance and capacitance, the target impedance also varies with frequency. Digital signals are actually composed of a superposition of an infinite number of Fourier harmonics, although ~75% of the power density is contained between below the signals knee frequency (approximately 0.35 divided by the signal rise time). 

This means the PDN’s impedance should be flat over the broadest possible frequency range. In a practical situation, this is very difficult, but as long as the PCB impedance spectrum is below your target impedance within the relevant frequency band, then the voltage ripple you see will be lower than your target value. The real impedance of a PDN will have a complicated spectrum composed of resonances (low impedance) and anti-resonances (high impedance). An example is shown below:

 

Capacitors on a VRM

Example impedance spectrum for a PDN in a PCB. This complex spectrum arises due to parasitic capacitance and inductance in your PCB.

 

Power Integrity in a PDN Topology Simulation

So what does this mean for signal and power integrity? If you look at the equation above, we see that if the target impedance value is large, then you will have a large voltage ripple. You should be able to naturally see that a digital signal with a knee frequency corresponding to a PDN impedance anti-resonance can cause ringing, i.e., an underdamped transient oscillation on the power bus. When a component switches repeatedly, such as with a clock, you are now driving a forced oscillation on the power bus. If the driving frequency matches a PDN impedance anti-resonance, then you will have a strong voltage fluctuation seen on the power bus.

If a large number of ICs switch simultaneously, this causes the voltage seen by all other ICs to change significantly. This can cause unintentional switching in digital ICs, which significantly increases BER. If your power bus also provides power to analog ICs, this forced oscillation will be copied onto the output of your analog ICs. This is one reason why some designers will place a large inductor or ferrite before the power pin on DAC/ADC ICs as this helps filter out the transient oscillation before it reaches the power pin. Be careful with any components used for decoupling (including capacitors!) as parasitics cause these components to behave as RLC circuits, which should be accounted for in your simulations (see below).

What You Should Analyze in a PDN Topology Simulation

First and foremost, you should examine IR drop throughout your PDN using a use a power delivery network analyzer. This will tell you how much voltage is dropped due to DC resistance in your power plane/rails, and your ground plane. This can also help you identify potential hot spots in your board. You can do this directly from your layout.

Second, you need to design your PDN to prevent ringing and ensure the impedance spectrum is flat over the relevant frequency bandwidth. A post-layout simulation tool can help with this, but in this designers opinion, it is better to do this during circuit design with a SPICE-based simulator. The issue with ringing mentioned above can be solved in two ways:

  • Increase the parasitic capacitance or decrease the parasitic inductance of your PDN. In other words, change the desired dimensions of your power plane. This will adjust the damping constant and natural frequency of your PDN so that the transient response is closer to the critically damped regime, which will eliminate the transient oscillation.

  • If you are working with digital ICs and you can’t critically damp the oscillation in the power bus, then increase the PDN’s lowest anti-resonance frequency so that it is much higher than the knee frequency for your signals. This could broaden the region where the PDN impedance is flat.

  • Add decoupling/bypass capacitors with sufficiently high self-resonance frequencies to the PDN. Note that this effectively increases the PDN’s parasitic capacitance. However, capacitors have self-resonance due to their own parasitics, which can again change the conditions for resonance.

 

Capacitors and other discrete components for a PDN topology simulation

Be sure to account for parasitics in a PDN topology simulation if you use capacitors and inductors for decoupling.

 

Once you’ve included decoupling networks, bypass capacitors, and accounted for parasitics on power rails in your schematic, you’ll need to calculate the natural and resonance frequencies of your PDN by simulating an input current impulse or using an AC frequency sweep. You must also account for the self-resonance frequencies of any capacitors and inductors used in your PDN. High quality component models might include this information, but you should still check to see whether this is the case in your circuit simulations. If your PDN includes vias, it is also a good idea to include via circuit models in your PDN as any vias will affect the impedance spectrum you’ll observe at GHz frequencies.

Any PDN topology simulation can be complicated, but the process for designing your PDN to ensure power integrity is easy when you use the right PCB design and analysis software package. The simulation tools in OrCAD PSpice Simulator and the full suite of analysis tools from Cadence allow you to simulate the behavior of your PDN and prevent common power integrity problems in advanced devices.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.

About the Author

Cadence PCB solutions is a complete front to back design tool to enable fast and efficient product creation. Cadence enables users accurately shorten design cycles to hand off to manufacturing through modern, IPC-2581 industry standard.

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