Remove unused sections of plated through holes in high-speed designs to improve signal integrity on your designs.
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Baby Steps to Self-Driving-Cars
Most of us spend a good bit of time getting from place to place. Turning driving into work-time would add billions of productive hours to our collective lives. Work-time can be defined in many ways...
Lost in Translation: Solving Common Issues in High-Speed Design
Creating a printed circuit board with high-speed design functionality is no small feat. The more complex a PCB design becomes, the higher the chances are of running into...
Signal Integrity Analysis of Serial Data Channels
Overview of BER analysis for DDR4 Interfaces with SystemSI.
DDR4 Power-Aware Signal Integrity Adopting Serial Link Simulation Techniques
An demonstration of BER analysis for DDR4 Interfaces with SystemsSI.
Notes on Near Field Communications
NFC is a touch-and-go standard for sharing a few packets of data with another device that is in close proximity. How close?
The Ethernet is Coming For Your Ride
Automotive Ethernet. It really is a thing. Our cars will have to outsmart our phones if we’re going to hand over the reins in any meaningful (and safe!) way.
What You Need to Know About Picking a Power Supply for a Gaming PC
Beginners often make the mistake of settling for a cheap off-brand unit that boasts a large power supply rating. Others might overspend on a larger power supply rating to ensure they’ll have enough...
Tips for Routing Mixed Signal PCBs
Your list gets even longer when working with mixed signal circuits, so here are some tips to get you started on the right track with your design
Five Tell-Tale Signs of a Bad Power Distribution Network
Given multiple power supply voltages, PCBs with high layer counts, or split planes, designing a PDN can be a daunting process. Here are five signs that a PDN needs some design adjustments.
DDR Bus Design for PCB Engineers
Last summer, Cadence and Micron prototyped the first IP interface in silicon for a preliminary version of the DDR5-4400 IMC. The new chip clocked in at an impressive....
Double check your DFM rules before signoff with a forced batch check of all rules for your whole design. If you do find something awry, it’s easy to locate and fix in your design.
Real-Time DFT Rules
Easily ensure test points are accessible in your designs.
Z-Axis and Package Pin Delay
Measure from true signal origin to end point through vias and through packages, not just the etch, so you can get timing right and ensure signal performance.
Real-Time Coupling Analysis
Easily and quickly identify coupling issues without always having to rely on the SI expert.
Real-Time Dynamic Differential Pair Routing
Easily meet length and phase pin-to-pin constraints as traces bend without creating electrical issues.
Real-Time Placement Analysis
Visual indicators of length constraints help you meet delay propagation and total etch length goals when placing components.
Real-Time Route Analysis
Real-time interactive checks help you easily find and fix common route quality issues that manufacturing DRC signoff checks miss.
Real-Time Impedance Analysis
Easily and quickly identify impedance discontinuity issues visually, without simulation models or extensive signal integrity expertise.
The Effect of PDN Elements on Impedance
Modern PCB designers are faced with an interesting challenge. The customer demands high speed PCB components with low impedance power networks. But high signal components tend to draw a lot of power..
Techniques for Optimizing Return Paths