DDR Bus Design for PCB Engineers

December 19, 2018 OrCAD PCB Solutions

DDR

source: wikipedia

DDR Bus Design for PCB Engineers

Last summer, Cadence and Micron prototyped the first IP interface in silicon for a preliminary version of the DDR5-4400 IMC. The new chip clocked in at an impressive 4400 megatransfers per second (MT/sec), 37.5 percent faster than commercial DDR4 memory on the market.

While it will be some time before DDR5 chips start appearing in mainstream devices, PCB designers already have the tools they need to start developing SoCs that take advantage of the new hardware. 

New to DDR bus design and not sure where to start? In this post, we’ll cover the basics so that you’ll be able to hit the ground running with our high speed PCB design for signal integrity training course.

What is a computer bus?

A computer bus is simply a group of electrical lines or wires that can carry computer signals. In a DDR bus, you usually have a controller which serves as the master, and any number of DRAM chips (e.g. DIMM) which serve as slaves. The electrical lines themselves can be categorized based on their function:

  • Power lines provide electrical power to attached components

  • Command lines provide control for the synchronization and operation of the bus and its modules.

  • Address lines designate the source or destination of a data signal.

  • Data lines carry data or instructions between components.

Keeping these generalized roles in mind, let’s take a look at how the lines are designated in a DDR bus.

DDR bus fundamentals

In a DDR bus, lines are typically labeled like this:

  • CA: The command/address lines are unidirectional with the output at the controller and the input at the DIMM.

  • CLK: This is the clock signal, a square wave that helps with timing and control.

  • DQ: This is the data line that will actually transfer bits on every leading edge and falling edge of the clock signal. The data line is bidirectional.

  • DQS: Data strobe encoding is used to help with timing, improve jitter tolerance, and allow for easy clock recovery.

Data strobe encoding allows you to have individual read/write signals, allowing your bus to exist in three states: active read, active write, and a bus free state. We’ll go into more detail in how this all works in the next section.

Putting it all together: how does a DDR bus work?

Before you can design DDR bus, it helps to understand how it works. Each DIMM has a bidirectional data line (DQ) to the controller. These data streams are accompanied by a strobe signal (DQS).

During write, data flows from controller to the DIMM. The controller launches a data signal halfway between two DQS transitions.

During read, data flows from DIMM to the controller. The DIMM launches a data signal in line with with DQS (it is controller’s job to delay data and/or strobe appropriately to latch in the data using the DQS)

The interface as a whole is operated by the common clock, command, and address lines that link the DRAM ICs to the controller. DDR3 introduced a “fly-by” topology, which connects the DRAM chips on the memory module in series and ends in a grounded terminal point that absorbs residual signals. This design allows for better signal quality at higher speeds.

The Key to DDR Bus Design? It’s all in the timing

There are three important timings in DDR bus design:

  • DQ is sampled by the DQS, and needs to meet input setup and hold time requirements at the DRAM. Since data signal needs time to stabilize, it is launched halfway between two DQS transitions. Propagation delays must be factored into the layout and kept similar across all lanes.

  • CA signal is sampled by the CLK, and needs to meet setup and hold time requirements at the DRAM. In order for the CA signal to be stable during the CLK’s rising edge, it must be delayed by an amount equal to the clock. In other words, the delay for the address and the clock must line up at any given DRAM.

  • DQS and CLK need to line up at each DRAM. Fly-by routing of CA and CLK incorporated in DDR3+ adds complexity to design in that it causes increasing clock skew with the data bus at every DRAM down the line. Timing must accommodate for delays caused by the physical reality of the architecture.

Conclusion

This article barely scratched the surface of DDR bus design. Changing voltages and currents, high speed signals, crosstalk, and EMI/EMC considerations further complicate the job. Fortunately Cadence offers a broad portfolio of tools to help you work on your next DDR IP design.

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