OrCAD datasheets

Allegro Design Entry Capture

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Cadence Schematic Capture Technology By combining schematic design capture technology, based on OrCAD ® Capture, with extensive simulation and board layout technology, Cadence helps you capture design intent correctly the first time. Whether used to design a new analog circuit, revise a schematic diagram for an existing PCB, or design a digital block diagram with an HDL module, Allegro ® Design Entry CIS allows designers to enter, modify, and verify connectivity for the PCB design. It also integrates with a robust Component Information System (CIS), promoting reuse of preferred compo- nents and known good-part data. The easy-to-use technologies allow designers to focus their creativity on design capture rather than tool operation. The hierarchical schematic page editor combines a Windows user interface with functionality and features specifically for design entry tasks and for publishing design data. Centralized project manage-ment provides seamless interchange of schematic data for circuit simulation, board layout, and signal integrity analysis. A configurable design rule check (DRC) mechanism helps eliminate costly engi-neering change orders (ECOs). A basic bill of materials (BOM) can be created from data contained in the schematic database. Benefits • Provides fast, intuitive schematic editing • Boosts schematic editing efficiency through design reuse • Automates the integration of field programmable gate arrays (FPGAs) and programmable logic devices (PLDs) • Makes changes quickly through a single spreadsheet editor • Imports and exports every commonly used design file format • Integrates with a robust Component Information System (CIS) to promote reuse of preferred, current parts Features Schematic editing Subcircuit reuse—without having to make multiple copies—increases schematic editing efficiency. Using hierarchical blocks, designers simply reference the same subcircuit multiple times. Automatic creation of hierar- chical ports eliminates potential design connection errors. Ports and pins can be updated dynamically for hierarchical blocks and underlying schematics. Added navigation utilities recognize block boundaries and acces- sibility using keyboard shortcuts. Ease of use The schematic page editor combines an intuitive user interface with functionality and features that enhance usability and speed for accomplishing design tasks and publishing design data. The autowire capability, for example, automates the often tedious and time-consuming task of wiring signal pins. Wiring between component pins is as simple as selecting a starting pin and a desti- nation pin and letting the software To develop innovate products in narrow market windows, system designers face far greater challenges than simply capturing connectivity using schematics and sending designs into layout. They must use optimal library parts, reuse sections of previous designs to reduce risk and shorten development time, add constraints early to eliminate iterations, and perform simulation and signal integrity analysis to ensure desired operation. Cadence ® schematic capture technology offers a comprehensive solution for entering, modifying, and verifying complex system designs quickly and cost-effectively. Cadence Schematic Capture Fast, intuitive design entry with reuse of preferred, current parts

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