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Sigrity SystemSI Technology

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Benefits Use Sigrity SystemSI technology to: • Perform detailed SI analysis of high-speed parallel buses and serial links • Perform die-to-die analysis pre-layout, post-layout, or anywhere in between • Verify interfaces will be compliant with interface performance standards • Concurrently evaluate SI effects such as losses, reflections, crosstalk, and simultaneous switching outputs (SSO) • Observe the impact of non-ideal power delivery system effects on system behavior • Improve design quality by identifying potential SSO problems in parallel buses • Develop, test, and utilize IBIS AMI TX and RX models for serial link analysis • Quantify the bit error rate (BER) and performance of complex SerDes channels • Reduce costs and time by identifying potential problems early Features Parallel Bus Analysis approach Today's high-speed bus interfaces, such as DDRx memory designs, are characterized by tight timing margins and analysis requirements that cross chip, package, and board structures. With the Sigrity SystemSI Parallel Bus Analysis approach, you get support for concurrent simulation that accounts for the effects of dielectric and conductor losses, reflections, inter-symbol interference (ISI), crosstalk, and simultaneous switching noise (SSN). This is essential for emulating real hardware behavior. Serial Link Analysis approach Assuring robust operation of high-speed serial links is challenging as data rates climb into the double- digit multi-gigabit realm. The Sigrity SystemSI Serial Link Analysis approach Cadence ® Sigrity ™ SystemSI ™ signal integrity (SI) solutions provide a comprehensive and flexible SI analysis environment for accurately assessing high-speed, chip-to-chip system designs. A block-based editor makes it easy to get started. The solutions support industry-standard model formats and automatically connect the models. With a unique combination of frequency domain, time domain, and statistical analysis techniques, you can be confident of achieving robust parallel bus and serial link interface implementations. Sigrity SystemSI Signal Integrity Solutions Accurately assess high-speed, chip-to-chip system designs Figure 1: Simulation results for a DDR3 interface including a memory controller and SDRAM

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