Regarding the Use of Core Vias in a PCB Design

A popular answer to a high density interconnect (HDI) problem is to start with a simple printed circuit board and then proceed to add on layer after layer. This is known as a sequential lamination process. For the sake of balance, the layers are always added to the top and bottom in pairs. We have a notation that we use to describe the sequence.

A typical example would be a board that starts with N number of layers in the initial pressing and has three additional lamination steps after that. Each additional pressing adds two layers, one above and one below the previous step. The shorthand for that type of construction is 3+N+3 or simply a 3N3 stack-up.

We could get more detailed and substitute the actual number of layers in the first pressing for the N and call it, for instance, a 3+4+3 board for an even ten layers. The fact is that the fabricator is more concerned about how many layers get added afterwards than how many are used in the first step.

Figure 1. Image Credit: Author - Copies of this 14-layer 3+N+3 board could be assimilated into a 42 layer board as an instance of what is possible with advanced stack-ups. 

The three is not a random number. The fab shops that cater to the HDI market have the 3N3 board as their sweet spot. So how does one tune a factory to build a specific stack-up? It’s an equipment thing. Panels go through the etching and plating tanks with a short dwell while the chemical processes do their thing. Drilling, especially mechanical drilling, is a little slower than some of the other batch processes such as screen printing.

So, for each plating line, there are four drills and one printer. In between those two things are some of the most expensive pieces of equipment in the factory. Those items would be the presses. Or, likely in the case of a smaller shop, the press. The press is the bottleneck. It is the main reason that sequential build up takes longer and costs more. Arrange a tour of your local vendor. The ratio of presses to drill stations will be a tell of whether they are focused on through-hole or high density boards.

A shop that has enough bandwidth through the presses can deliver on the 3N3 board while keeping the other parts of the factory going at capacity. This level of technology is sufficient for most applications. Smartphones will require a stack of micro-vias all the way through the board. This is a function of their chip set and the seriously tight packaging to make way for the battery. Their factory floor will reflect those needs.

The Core of the Matter - It Starts With a Through-Hole 

The “simple board” is complete except for the lack of soldermask and silkscreen. The core will be at least two layers but often more. We talk about core and prepreg materials but this is a slightly different definition of ‘core’ than that. Our core can be two layers in which case there are overlapping definitions. We would still call it a core even when it is a core plus additional layers of prepreg. What eventually becomes the core via will start as a hole through a stack with multiple sheets of core material if that is what the design requires. The core in this case is the product of whatever comes out of the first lamination cycle.

Figure 2. Image Credit: Author - Increasing pin density drives the PCB to higher levels of technology. Sequential lamination boards are a mainstream answer in 2021

The materials for this initial building block can be woven glass for the completely rigid constructions or that plus polyimide for rigid/flex scenarios. In any case, the mechanically drilled holes in the core are filled with resin of the sort that makes up the space between the glass fibers in the dielectrics of the board. After filling, they are capped with copper and the sequential lamination can begin.

Squeezing a Little More Out of the Core Via

Emphasizing the fact that a core via starts as a through-hole via, the same process of plating up is required to deposit copper in the hole. This translates to using the larger minimum air-gaps and line-widths consistent with what is found on the outer layers vs. typical inner-layer constraints.

Knowing that the thicker copper favores the wider geometries, it makes sense to dedicate these layers to power and ground nets who happen to also benefit from the thick copper and wide geometry. Naturally, the layers in between are the candidates for fine line routing.

When the layer count gets hectic, there are bound to be multiple sub-boards that are piled up such that core via spans are more like local elevators from a routing perspective. Grouping busses and associated power domains into dedicated sections will keep the cross contamination down on these epic high layer-count boards.

If the core is a multi-layer stack-up, it may be possible to create some micro-vias in the core section prior to adding the first additional pair of layers in the sequence. You just have to use a thin dielectric on the outer layers for the micro-via to be manufacturable. You get a micro-via that does not add a lamination cycle. That’s like finding money!

Figure 3. Image Credit: Author - a 1N1+ stack-up with a core via from layers 2-5 and the “free” micro vias from 2-3 and 4-5. Note that the through hole is technically for components rather than vias.

If you like money, you should avoid trying to stack a micro via in the same location as the core via. That is one of the worst DFM transgressions. The exact distance between the core via and the adjacent micro-via will vary. I’m guessing that if you ask around, the preferred outcome is that the two vias have a span between them that would be equivalent to the air-gap of differing nets. Normal via-to-via spacing for same-net spacing gives the vendor a wide path to success.

That kind of thinking can run you out of options in some cases. Many chips are just not built for low-key circuit boards.  Pushing it to the limit for same-net via spacing would be to have the capture pads for the blind/buried and core vias tangent to each other; touching but not overlapping.

Be careful with overcommitting the transition layer. It will be busy with little snow-man shaped via-pairs so it’s tempting to crowd them together. The real estate under a fine-pitch ball grid array (BGA) device can be rather precious so it may be wise to minimize their use under the device to those connections that pass through the board like to a bypass cap or some other compelling reason. Route away from the device on the layers that are accessible by way of the micro-vias and then make the jump with the bigger via where there is more room for them.

Stitching Vias For a Strong Return Path and EMI Suppression

Tending to the return paths will involve many locations where there is a pattern of ground vias. The sooner you get to those details the easier they are to implement. Wherever a trace goes through a transition, there should be a provision to tie the various reference planes together.

You may be called upon to create a thermal path through the board. Think about leaving some dielectric material behind to maintain a level of impedance and structural integrity. Start with a concentration around the source but spread out as the vias are linked towards the other side of the board. I’ve never done it but don’t see why you couldn’t use a thermal paste via filler to increase the dissipation factor.

 Lines of vias of any kind generate slots in the planes. Sometimes, you’re stuck and have to do it. A little effort in those cases may be enough to break the slot into two smaller ones. The freedom of movement for the core via is better than that of the vias that are anchored to specific pins. Staggering the way they break out helps avoid magnetic coupling. A via is happy when it has a void of its own as it passes through a plane. Married couples, AKA differential pairs are an exception, of course.

So, there you have it. Core vias are part of the foundation of a sequential build-up board. Their use implies that one or more layers of buried and blind vias will be in the mix. This is the mix that solves most HDI routing studies. Having one core via costs the same as having many so, if you're already going that route, go ahead and live a little.

About the Author

John Burkhert

John Burkhert Jr is a career PCB Designer experienced in Military, Telecom, Consumer Hardware and lately, the Automotive industry. Originally, an RF specialist -- compelled to flip the bit now and then to fill the need for high-speed digital design. John enjoys playing bass and racing bikes when he's not writing about or performing PCB layout. You can find John on LinkedIn.

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