It is an old proverb. (Aren’t all proverbs old by definition?)This time tested-piece of advice was not meant for the signal integrity crowd but, it makes sense: Timing is everything. Your circuits are designed to make things happen in the correct sequence. That is really the only way they work so, yeah, not much else has a chance to matter if we are outside of the timing budget.
We are lucky to have the technology that helps us manage timing constraints. X-nets, pin-pairs, and match-groups may seem a little daunting at first. Once mastered, these are fantastic tools for capturing, executing and verifying the most complex of designs.
A Little at a Time
Length matching begins with two in the digital domain. Sometimes, two traces are meant to be complementary mirror images of one another.The receiving pin pair makes a comparison of the two signals and decides the state of the function – a logical 1 (one) or a 0 (zero). Since both the positive and the negative traces feel the pain of having traveled the same basic path, the standard noise they pick up cancels out. A little comparator is sitting there at the far end and waiting for a call. It does its thing and we are left with the voltage difference between the two as the official logical state.
These differential pairs have some of the most strict timing parameters. You want the two pieces of information hitting the receiver at the same instant.Length matching is plus/minus a few thousandths of an inch between the two. Sometimes, that still isn’t enough. Suppose that along the way, one of the waveforms takes the inside line and gets a little ahead of its counterpart. Then it whizzes past a nasty little switch mode power supply that is about to go hot for a moment. When the second waveform hits and picks up noise that wasn’t there a millisecond ago. So, we have what we call dynamic phase tolerance. This is where we compensate for every turn in the pair by re-aligning the two traces with a small bump in the one that took the shorter route. Static phase tolerance is when we just consider the overall length and do the compensation near the driver pins.
Aside from that, our diff-pairs come in two flavors, tightly coupled and loosely coupled. Tightly coupled lines happen when the air gap between the two traces is the same as or less than the line-widths. Loosely coupled lines can have two, three or even four times the trace width of the gap. This has more to do with impedance and noise rejection than actual length, but note that loosely coupled lines will get further out of phase because of the exaggerated shortcuts. The good news is that we can get away with more uncoupled length with the wider spacing to start with. Those little phase-tuning bumps add up.
Most of the usual protocols make use of differential pairs. These include PCI, USB, MIPI (cameras) as well as some good old analog applications. Maybe you have seen the back of an amplifier that has balanced and unbalanced outputs. Balanced outputs are differential and are known for their ability to work in noisy environments and over longer runs.
Some audio gear with both balanced and unbalanced I/O
A Step Up
We have all seen the “spaghetti” of serpentine traces winding from the SOC to the memory chip(s). Some of you might even be triggered when an artist tries to portray a proper circuit board. You are not alone. Yikes! Predictably, data rates and bandwidth go up with each new generation. Then the length requirements have been getting even more restrictive.
A rule of thumb is that when there are fewer data lanes, each one is carrying more data and needs more care. Flash memory protocols like SPI, UFS and EMMC tend to serialize the data over fewer lines. You have about four pairs, a clock, and a reset.We match the pairs to themselves first and tightest. Then, the pairs are matched to each other along with the clock that sets the nominal length target for all. A set of tight requirements are nested within an overall budget that is a bit looser.
This theme expands with another type of memory; random access or RAM. DDR is the shorthand for Double Data Rate. What that means in practice is that we are interrogating the device when the clock swings from zero to one and again when it goes back down to zero in its continuous oscillation. (To be fair to this topic would require about 10,000 words.)
All the system is going to tell you is that the clock is out of phase with itself while being too long AND too short...
We divide a river of traces into groups. Typically, there are eight members of each group of Address and Data lines. Those are shepherded by a variety of control, command and clock lines that ride on top of the address and data groups. The number of groups of eight depends on the amount of memory but count on four lanes of each per memory chip. These 8-bit “byte” lanes register their value in a cascading sequence and need decent control over timing within the group. From group to group, there is more latitude.
Again, the overall length target is determined by the clock which is itself a differential pair for this application. So you can route all of the connections and then start sliding the clock pair to find that it is not the correct length between the positive and negative traces. Furthermore, some of the individual members of the associated byte lanes may be too short and need to serpentine. Then, there is the outlier trace that goes to the far corner of the memory device, and it is too long for the current length of the clock
All the system is going to tell you is that the clock pair is out of phase with itself while being too long AND too short for everything else.You are going to want the constraint manager open on a second screen if possible. Analyzing the data will reveal the long and short of it which is a lot more efficient than merely flailing away at the slide command.
guru (Small g) Wisdom Time:
Find the longest member of the group and see if you can cut some corners to make it shorter. Note the “rubber-band” traces on the right of this screen capture. You might do this with all of the traces that are longer than the clock pair. If that solved the length errors on the long side, see if you can shorten the clocks to the point just before it becomes too short to meet the mask. If, on the other hand, the clock still isn’t long enough, the add some serpentine until it matches the length of the longest line minus the allowable tolerance. These things do not have to be the exact same length. Use the available slop to decrease the amount of serpentine for the naturally short lines. That is the most elegant solution.
Timing constraints set the bar for digital circuits to the same degree that impedance drives the analog world. We still want to avoid impedance mismatches in our high-speed circuits. Don’t route over gaps in adjacent plane layers. Oh yeah, have them plane layers and stitching vias. Route these length-matched traces as soon as possible in the design cycle. You will want to know if you have sufficient layers to keep everything tidy. Using lower-cost construction of the stack-up can put you on GND-SIG-SIG-GND configurations. You just have to be careful not to cause broadside coupling between the signal layers.
Some traces are width controlled and only need to be kept as short as possible. Other analog traces are used as delay lines and will meander a bit. Then, there are the digital traces that are constrained in pairs and overlapping groups of different sizes with different requirements. Managing all of these can be done manually. If that is the plan, I would recommend getting those wrist braces for the inevitable carpal tunnel issues. In the long run, knowledge of the spreadsheet that governs the rules will be a much better design proposition. It’s not a new proverb. Timing is everything!
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